Understanding and implementing the ATAPI interface on a microcontroller

This page is work in progress!

Contents

Introduction

This page contains my structured notes on the interface and protocol used by IDE disc drives, which I have studied in order to implement it myself. Writing this page both improves my own knowledge and provides a educational resource for others interested in creating a DIY implementation.

The current intended scope of this page is enough to send ATAPI commands to an optical disc drive for track control and information. I am deliberately choosing to not concern myself with DMA (direct memory access), and to only use PIO (programmed input/output) as this is sufficient for my needs and is just easier to work with. This is a summary of information I pulled together from various sites, resources and specifications.

Disambiguation: There are a few names used interchangeably for the 40-pin interface. The big three are:

• IDE - integrated drive electronics, the original name before being absorbed into the ATA standard
• ATA - AT attchment, the "official" name
• PATA (parallel ATA, retroactively termed after the introduction of SATA).

Physical layer

Below is the pinout of the 40-pin connector used by IDE devices:

Table 1. IDE pinout

Signals with a n prefix are active low

Table 2. Signal descriptions

ATA

ATA devices contain two blocks of 8 registers each which are collectively refered to as the "task file". The task file is accessible over the IDE bus. A register is selected using the A0 - A2 pins, and a block is selected using either one (but not both) of nCS0 or nCS1. Register functions are dependent on whether the address is being written or read. Vacant cells in the address and CS columns have a value of zero. The zeroes were omitted for readability.

Table 3. contains the contents of the task file for non-packet ATA devices such as hard disks. These registers are used by a host (e.g. IDE controller card) to perform read and write operations. This is useful context to know, but the task file for packet devices (CD and DVD drives) looks different.

Table 3. ATA task file map

ATAPI

ATAPI (ATA packet interface) is an extension of ATA used in optical drives that allows SCSI commands to be given to ATA devices by transmitting them in packets. Like ATA, ATAPI devices also have a task file addressable over the 40-pin physical interface, but the register functions and purposes are different. Confusingly, some DIY implementations, such as ATAPIduino, refer to these by the ATA names.

Table 4. ATAPI task file map

The control block contains various registers that are reserved for future use or are not used by ATAPI. Only one register in this block is used, at address 0b110. Writing to this register allows for "Device Control" as per its name, and according to SFF-8020i (the ATAPI specification), can be used to initiate a soft reset, or enable/disable the generation of interrupts on the INTRQ pin. Reading this register gives "Alternate ATAPI Status", which has the same value as "ATAPI status" in the command block, but reading the alternate status does not clear or acknowledge an interrupt. It may be possible to reduce a DIY ATAPI implementation by one pin & signal by choosing to not need to address the control block, if interrupts and soft resets will not be used.

The taskfile is used by ATAPI devices for status indication and low-level control of the device, but any CD/DVD related functionality is performed by sending commands as SCSI packets.

ATAPI task file register descriptions

ATAPI Error register

Sense key: 4-bit value indicating the nature of the error. See page 183 of SFF-8020i
MCR: media change requested
ABRT: aborted command
EOM: end of media detected
ILI: illegal length indication

ATAPI Features register

DMA: when 1, data for the Command will be transferred by DMA.
OVERLAP: when 1, the drive may release the ATA bus before the current command completes.

ATAPI interrupt reason register

RELEASE: indicates that the drive has released the ATA bus before completing the command in progress.
The states of the IO and CoD bits in this register, and the DRQ bit of the status register give the interrupt reason. Refer to Table 15 of SFF-8020i for a look-up.

ATAPI byte count LO & HI registers

Only used for PIO (as oppposed to DMA). Indicates the size of a transfer, in number of bytes.

Drive select register

When the DRV bit is 0, then Device 0 (master) is selected. If 1, then Device 1 (slave) is selected.

ATAPI status register

BSY: Set whenever the drive is accessing the command block.
DRDY: Indicates that the drive is able to respond to an ATA command.
DMA READY: Indicates that the drive is ready to start a DMA transfer.
SERVICE: signals that a drive is requesting service or interrupt. Set when an interrupt is requested, cleared when a Service (opcode 0xA2) command is issued.
DRQ: Data request. Indicates that the drive is ready for a data transfer.
CORR: Indicates that a correctable error occurred.
CHECK: Indicates that an error occured during execution of the previous command.

ATA Command register

An 8-bit opcode corresponding to a command is written to this register, instead of individual bits having their own purposes.

Alternate status register

Contents are the same as the status register, but reading this register does not clear/acknowledge an interrupt.

Device control register

SRST: Software reset
nIEN: When 0, enables interrupts. When 1, the INTRQ pin is high-impedance.

Implementing a physical interface

The microcontroller or other component used for the ATA signalling must signal at 5 volts. If this is not the case, then logic level shifters will be required.

For ATAPI, the entire width of the data bus is required (16 IO pins). It is most convenient to allocate an entire IO port each for the data bus' upper and lower bytes, or if possible, for the entire bus if you are working with 16-bit IO ports. This way, direct port manipulation can be used to read and write data (a single value can be written/read to/from a port) instead of having to individually handle each bit using functions like digitalRead() and digitalWrite().

3 pins are required for the address bus, 2 for the chip select signals, and 2 for the read and write strobes. It is also useful to dedicate a pin for the ATA reset signal.

This minimal signal set requires 24 IO pins.

It may be desirable to use the INTRQ signal from the drive in order to trigger an interrupt, so this signal may be optionally routed.

Since DMA is ignored in this article, any DMA related signals are also ignored.

Writing and reading the task file

ATAPI drive detection

A signature is placed in the "byte count HI" and "byte count LO" registers at power up and reset. The signature will also be placed when carrying out the "IDENTIFY PACKET DEVICE" command (also called "ATAPI IDENTIFY DEVICE"). Source

1. Select the drive by setting the "Drive Select" register appropriately
2. Read the "byte count HI" and "byte count LO" registers and inspect the values for the ATAPI signature.
   Byte count LO should contain 0x14, and Byte count HI should contain 0xEB.
   For non-ATAPI devices, the values will instead be 0x00 and 0x00 respectively.

ATAPI device identification

1. Write the IDENTIFY PACKET DEVICE command (opcode 0xA1) to the ATA command register
2. This command will insert 255 data words into the data register. Reading the data register will cause the next data word to be placed in sequence.
3. Refer to page 62 of SFF-8020i for the contents of each data word. The drive's packet length, firmware and model number can all be identified from the output of this command. The data words must be read in sequence from the beginning until reaching the one that is required.
4. Continue reading the output until all words have been read and the command completes.

Algorithm for issuing an ATAPI packet

Depending on the drive, a packet will have a length of either 12 bytes or 16 bytes. For devices that require 16-byte packets, it is sufficient to issue a 12-byte packet and then issue 4 bytes that are equal to 0x00.

ATAPI packets consist of 12 or 16 bytes, and it may be tempting to think that they are issued one byte at a time, using the lower half of the 16-bit data bus. In reality, packets are transferred to a drive 2 bytes at a time using the full width of the data bus. For a drive with packet length of 12 bytes, the packet will be issued in 6 write cycles, with evenly-ordered bytes being placed in the lower half and odd-ordered bytes being placed in the upper half.

For example:
During the first write, D7 to D0 of the data bus will contain byte 0, and D15 to D8 wil contain byte 1.
During the second write, D7 to D0 will contain byte 2, and D15 to D8 will contain byte 3.

Issuing a packet

1. Write the PACKET command (opcode 0xA0) to the ATA command register
2. Poll the status register and wait for DRQ to be set
3. Form a data word (16-byte unit) for each of the packet's byte pairs, and write to the data register

Further reading & sources

Page created: 22MAR2026
Last modified: 14MAY2026