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MROM64 working principle
A higher capacity ROM chip is used to replace the existing ROM chips, which means that there are additional address pins on the replacement ROM that the C64 is oblivious to and does not use.
These additional address pins can be used to apply an offset to the requested address and select data in a different location in the ROM chip, thereby selecting a distinct bank of data. The number of
redundant additional address pins determines how many of these banks can exist and be selected.
Consider the following simplified case:
Sven Petersen's C64-CHARSET-Adaptor-Switch replaces the Character ROM, which has 12 address pins (labelled A0 - A11),
with a "512" type ROM chip, with 16 address pins (labelled A0 - A15). The "512" type ROM has 4 address pins above the required address range, and these pins can be set to logic 1 or 0 to alter the base
offset of the ROM's address and select one of 16 banks containing distinct character sets. (16 possible offsets because 2^(4) ).
I first devised a memory map for the MROM64C, which would then help me create a logic circuit that presents the correct data bank based on what the user has set and what the C64 expects.
I refer to the 010's address pins as R0-R16, using R instead of the more conventional A, to differentiate from the C64's bus.
This means that, for example, R13 in refers to pin A13 of the 010 ROM.
Empty cells represent a binary zero, and are left empty for readability reasons.
| Address in 010 ROM | Contents | Bank size | R16 | R15 | R14 | R13 | R12 |
| 0x00000 | Font 0 | 4K | | | | | |
| 0x01000 | Font 1 | 4K | | | | | 1 |
| 0x02000 | Font 2 | 4K | | | | 1 | |
| 0x03000 | Font 3 | 4K | | | | 1 | 1 |
| 0x04000 | Font 4 | 4K | | | 1 | | |
| 0x05000 | Font 5 | 4K | | | 1 | | 1 |
| 0x06000 | Font 6 | 4K | | | 1 | 1 | |
| 0x07000 | Font 7 | 4K | | | 1 | 1 | 1 |
| 0x08000 | Font 8 | 4K | | 1 | | | |
| 0x09000 | Font 9 | 4K | | 1 | | | 1 |
| 0x0A000 | Font 10 | 4K | | 1 | | 1 | |
| 0x0B000 | Font 11 | 4K | | 1 | | 1 | 1 |
| 0x0C000 | Font 12 | 4K | | 1 | 1 | | |
| 0x0D000 | Font 13 | 4K | | 1 | 1 | | 1 |
| 0x0E000 | Font 14 | 4K | | 1 | 1 | 1 | |
| 0x0F000 | Font 15 | 4K | | 1 | 1 | 1 | 1 |
| 0x10000 | BASIC | 8K | 1 | | | | transparent |
| 0x12000 | Kernal 0 | 8K | 1 | | | 1 | transparent |
| 0x14000 | Kernal 1 | 8K | 1 | | 1 | | transparent |
| 0x16000 | Kernal 2 | 8K | 1 | | 1 | 1 | transparent |
| 0x18000 | Kernal 3 | 8K | 1 | 1 | | | transparent |
| 0x1A000 | Kernal 4 | 8K | 1 | 1 | | 1 | transparent |
| 0x1C000 | Kernal 5 | 8K | 1 | 1 | 1 | | transparent |
| 0x1E000 | Kernal 6 | 8K | 1 | 1 | 1 | 1 | transparent |
The character ROM has a size of 4KB and the kernal and BASIC ROMs have a size of 8KB. As the kernal and BASIC ROMs are twice the size, they require an additional address pin.
Depending on whether the C64 is accessing the character set or kernal/BASIC, the user-selectable kernal and character bit combination must be passed through to the 010's R12-R16 pins,
while preserving the state of A12 during kernal/BASIC reads.
I made good use of Paul Falstad's circuit simulator in order to create a digital logic circuit that meets the requirement:
Click to download the circuit for use with Falstad's circuit simulator.
When the Kernal/BASIC ROM's chip select pin is high, the character ROM selection bits (labelled F0 to F3) are passed through to the 010 ROM chip. When this chip select pin is low,
the kernal selection bits and A12 from the C64's address bus are passed through.
When both kernalCS# and B#/K are low, then the BASIC ROM must be selected, which is done by setting one input to the AND gates low, which forces their output to be zero and thus forcing
selection of the BASIC ROM as appropriate.
When either one of the kernal or character set's chip select signals are low, then OE# (output enable) on the 010 must be set low. Either input to the AND gate will set the output low, causing
this to occur. The correct gate to use here is XNOR, but the case where both inputs are 0 can be ignored, because both inputs will not be 0 simultaneously. This also allowed me to use one less
chip, as I could use one quadruple AND chip, instead of needing another chip for a XNOR gate.
Page created: 18DEC2025
Last modified: 06JAN2026